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4012fa ltc4012/ ltc4012-1/ltc4012-2 features a pplications description high efficiency, multi-chemistry battery charger with powerpath control the ltc4012 is a constant-current /constant-volt- age battery charger controller. it uses a synchronous quasi-constant frequency pwm control architecture that will not generate audible noise with ceramic bulk capacitors. charge current is set by external resis- tors and can be monitored as an output voltage. with no built-in termination, the ltc4012 family charges a wide range of batteries under external control. the ltc4012 features fully adjustable output voltage, while the ltc4012-1 and ltc4012-2 can be pin-programmed for lithium-ion/polymer battery packs of 1-, 2-, 3- or 4-series cells. the ltc4012-1 provides output voltage of 4.1v/cell and the ltc4012-2 is a 4.2v/cell version. the device includes ac adapter input current limiting, which maximizes charge rate for a fixed input power level. an external sense resistor programs the input current limit, and the icl status pin indicates reduced charge current as a result of ac adapter current limiting. ideal diode control at the adaptor input improves charger efficiency. the chrg status pin is active during all charging modes, including special indication for low charge current. n general purpose battery charger controller n efficient 550khz synchronous buck pwm topology n 0.5% output float voltage accuracy n programmable charge current: 4% accuracy n programmable ac adapter current limit: 3% accuracy n no audible noise with ceramic capacitors n infet low loss ideal diode powerpath? control n wide input voltage range: 6v to 28v n wide output voltage range: 2v to 28v n indicator outputs for ac adapter present, charging, c/10 current detection and input current limiting n analog charge current monitor n micropower shutdown n 20-pin 4mm 4mm 0.75mm qfn package n notebook computers n portable instruments n battery backup systems efficiency at dcin = 20v l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and powerpath and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5723970. clp from adapter 13v to 28v 0.1f 5.1k 25m 3.01k 0.1f 6.8h 20f 33m infet 0.1f 2f 0.1f 6.04k 26.7k ltc4012 dcin acp chrg icl shdn ith prog cln boost tgate sw intv dd bgate to/from mcu gnd csp csn bat fbdiv v fb 20f power to system 4.7nf 32.8k 4012 ta01 12.3v li-ion battery 3.01k 301k + charge current (a) 0 70 efficiency (%) power loss (mw) 75 80 85 90 100 100 1000 10000 0.5 1 1.5 2 4012 ta02 2.5 3 95 part ltc4009 ltc4012 infet x dcdiv x pin name v out = 12.3v r sense = 33m r in = 3.01k r prog = 26.7k efficiency power loss t ypical a pplication
ltc4012/ ltc4012-1/ltc4012-2 4012fa a bsolute maxi m u m r atings dcin ............................................................C14v to 30v dcin to clp ................................................ C32v to 20v clp, cln or sw to gnd ............................. C0.3v to 30v clp to cln ............................................................0.3v csp, csn or bat to gnd ........................... C0.3v to 28v csp to csn ............................................................0.3v boost to gnd ........................................... C0.3v to 36v boost to sw............................................... C0.3v to 7v (note 1) o r d er i n f or m ation lead free finish tape and reel part marking* package description temperature range ltc4012cuf#pbf ltc4012cuf#trpbf 4012 20-lead (4mm 4mm) plastic qfn 0c to 85c ltc4012cuf-1#pbf ltc4012cuf-1#trpbf 40121 20-lead (4mm 4mm) plastic qfn 0c to 85c ltc4012cuf-2#pbf ltc4012cuf-2#trpbf 40122 20-lead (4mm 4mm) plastic qfn 0c to 85c ltc4012iuf#pbf ltc4012iuf#trpbf 4012 20-lead (4mm 4mm) plastic qfn C40c to 125c ltc4012iuf-1#pbf ltc4012iuf-1#trpbf 40121 20-lead (4mm 4mm) plastic qfn C40c to 125c ltc4012iuf-2#pbf ltc4012iuf-2#trpbf 40122 20-lead (4mm 4mm) plastic qfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ shdn , fvs0, fvs1 or v fb to gnd ............... C0.3v to 7v acp , chrg or icl to gnd .......................... C0.3v to 30v operating temperature range (note 2) ............................................. C40c to 125c junction temperature (note 3) ............................. 125c storage temperature range .................. C65c to 150c p in c on f iguration ltc4012 ltc4012-1 ltc4012-2 20 19 18 17 16 6 7 8 top view 21 gnd uf package 20-lead (4mm s 4mm) plastic qfn 9 10 5 4 3 2 1 11 12 13 14 15 cln clp infet dcin acp csp csn prog ith bat boost tgate sw intv dd bgate shdn chrg icl v fb fbdiv t jmax = 125c, ja = 37c/w exposed pad (pin 21) is gnd, must be soldered to pcb 20 19 18 17 16 6 7 8 top view 21 gnd uf package 20-lead (4mm s 4mm) plastic qfn 9 10 5 4 3 2 1 11 12 13 14 15 cln clp infet dcin acp csp csn prog ith bat boost tgate sw intv dd bgate shdn chrg icl fvs0 fvs1 t jmax = 125c, ja = 37c/w exposed pad (pin 21) is gnd, must be soldered to pcb
4012fa ltc4012/ ltc4012-1/ltc4012-2 e lectrical c haracteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. dcin = 20v, bat = 12v, gnd = 0v unless otherwise noted. (note 2) symbol parameter conditions min typ max units charge voltage regulation v tol v bat accuracy (see test circuits) ltc4012 c-grade i-grade l l C0.5 C0.8 C1.0 0.5 0.8 1.0 % % % ltc4012-1/ltc4012-2 c-grade fvs1 = 0v, fvs0 = 0v, i-grade fvs1 = 0v, fvs1 = 5v, i-grade fvs1 = 5v, fvs0 = 0v, i-grade fvs1 = 5v, fvs1 = 5v, i-grade l l l l l C0.6 C0.8 C1.1 C1.15 C1.25 C1.35 0.6 0.8 1.1 1.15 1.25 1.35 % % % % % % i vfb v fb input bias current v fb = 1.2v 20 na r on fbdiv on resistance i load = 100a l 85 190 i leak-fbdiv fbdiv output leakage current shdn = 0v, fbdiv = 0v l C1 0 1 a v bov v fb overvoltage threshold ltc4012 l 1.235 1.281 1.32 v bat overvoltage threshold ltc4012-1/ltc4012-2, relative to selected output voltage l 103 106 109 % charge current regulation i tol charge current accuracy with r in = 3.01k, 6v < bat < 18v (ltc4012) 6v < bat < 15v (ltc4012-1, ltc4012-2) r prog = 26.7k c-grade i-grade l l C4 C5 C9.5 4 5 9.5 % % % v sense = 0mv, prog = 1.2v C12.75 C11.67 C10.95 a a i current sense amplifier gain (prog ?i) with r in = 3.01k, 6v < bat < 18v (ltc4012) 6v < bat < 15v (ltc4012-1, ltc4012-2) v sense step from 0mv to 5mv, prog = 1.2v C1.78 C1.66 C1.54 a v cs-max maximum peak current sense threshold voltage per cycle (r in = 3.01k) ith = 2v, c-grade ith = 2v, i-grade ith = 5v l l l 140 125 195 325 250 265 430 mv mv mv v c10 c/10 indicator threshold voltage prog falling 340 400 460 mv v rev reverse current threshold voltage prog falling 180 253 295 mv input current regulation v cl current limit threshold clp C cln c-grade i-grade l l 97 96 92 100 100 103 104 108 mv mv mv i cln cln input bias current cln = clp 100 na v icl icl indicator threshold (clp C cln) C v cl C8 C5 C2 mv clp supply ovr operating voltage range 6 28 v v uvlo clp undervoltage lockout threshold clp increasing l 4.65 4.85 5.25 v v uv(hyst) uvlo threshold hysteresis 200 mv i clpo clp operating current clp = 20v, no gate loads 2 3 ma shutdown v acp ac present threshold voltage dcin C bat, dcin rising c-grade i-grade l l 350 300 500 650 700 mv mv v acp(hyst) acp threshold hysteresis voltage 200 mv v il shdn input voltage low l 300 mv v ih shdn input voltage high l 1.4 v
ltc4012/ ltc4012-1/ltc4012-2 4012fa e lectrical c haracteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. dcin = 20v, bat = 12v, gnd = 0v unless otherwise noted. (note 2) symbol parameter conditions min typ max units r in shdn pull-down resistance 40 k i clps clp shutdown current clp = 12v, dcin = 0v shdn = 0v l 15 350 26 500 a a i leak-bat bat leakage current shdn = 0v or dcin = 0v, 0v csp = csn = bat 18v l C1.5 0 1.5 a i leak-csn csn leakage current shdn = 0v or dcin = 0v, 0v csp = csn = bat 20v l C1.5 0 1.5 a i leak-csp csp leakage current shdn = 0v or dcin = 0v, 0v csp = csn = bat 20v l C1.5 0 1.5 a i leak-sw sw leakage current shdn = 0v or dcin = 0v, 0v sw 20v l C1 0 2 a intv dd regulator intv dd output voltage no load l 4.85 5 5.15 v ? v dd load regulation i dd = 20ma C0.4 C1 % i dd short-circuit current (note 5) intv dd = 0v 50 85 130 ma switching regulator i ith ith current ith = 1.4v C40/+90 a f typ typical switching frequency 467 550 633 khz f min minimum switching frequency c load = 3.3nf 20 25 khz dc max maximum duty cycle c load = 3.3nf 98 99 % t r-tg tgate rise time c load = 3.3nf, 10% C 90% 60 110 ns t f-tg tgate fall time c load = 3.3nf, 90% C 10% 50 110 ns t r-bg bgate rise time c load = 3.3nf, 10% C 90% 60 110 ns t f-bg bgate fall time c load = 3.3nf, 90% C 10% 60 110 ns t no tgate, bgate non-overlap time c load = 3.3nf, 10% C 10% 110 ns powerpath control i dcin dcin input current 0v dcin clp l C10 60 a v fto forward turn-on voltage (dcin detection threshold) dcin-clp, dcin rising l 15 60 mv v fr forward regulation voltage dcin-clp l 15 25 35 mv v rto reverse turn-off voltage dcin-clp, dcin falling l C45 C25 C15 mv v ol(infet) infet output low voltage, relative to clp dcin-clp = 0.1v, i infet =1a C6.5 C5 v v oh(infet) infet output high voltage, relative to clp dcin-clp = C0.1v, i infet = C5a C250 250 mv t if(on) infet turn-on time to clp-infet > 3v, c infet = 1nf 85 180 s t if(off) infet turn-off time to clp-infet < 1.5v, c infet = 1nf 2.5 6 s float voltage select inputs (ltc4012-1/ltc4012-2 only) v il input voltage low 0.5 v v ih input voltage high 3.5 v i in input current 0v v in 5v C10 10 a indicator outputs v ol output voltage low i load = 100a, prog = 1.2v 500 mv i leak output leakage shdn = 0v, dcdiv = 0v, v out = 20v l C10 10 a i c10 chrg c/10 current sink chrg = 2.5v l 15 25 38 a
4012fa ltc4012/ ltc4012-1/ltc4012-2 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc4012c is guaranteed to meet performance specifications over the 0c to 85c operating temperature range. the ltc4012i is guaranteed to meet performance specifications over the C40c to 125c operating temperature range. note 3: operating junction temperature t j (in c) is calculated from the ambient temperature t a and the total continuous package power dissipation p d (in watts) by the formula t j = t a + ( ja ? pd). refer to the applications information section for details. note 4: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to gnd, unless otherwise specified. note 5: output current may be limited by internal power dissipation. refer to the applications information section for details. t est c ircuits ? ? ? + 9 13 12 1.2085v 1.2085v target prog v fb ith 40012 tc01 ltc4012 0.6v ea from icl (clp = cln) ? + ltc1055 ? ? ? + 11 13 12 1.2085v target varies with fvso,1 prog bat ith 40012 tc02 ltc4012-1 ltc4012-2 0.6v ea from icl (clp = cln) ? + ltc1055 e lectrical c haracteristics
ltc4012/ ltc4012-1/ltc4012-2 4012fa battery load dump battery voltage (500mv/div) load state time (1ms/div) clp = 20v v out = 12.3v 4012 g06 disconnect reconnect 3a 2a 12.1v 1a 1a t ypical p er f or m ance c haracteristics efficiency at dcin = 20v, bat = 8v v fb line regulation charge current (a) 0 80 efficiency (%) power loss(mw) 85 90 100 100 1000 10000 0.5 1 1.5 2 4012 g01 2.5 3 95 power loss efficiency r sense = 33m r in = 3.01k efficiency at dcin = 20v, bat = 12v charge current (a) 0 80 efficiency (%) power loss(mw) 85 90 100 100 1000 10000 0.5 1 1.5 2 4012 g02 2.5 3 95 efficiency power loss r sense = 33m r in = 3.01k efficiency at dcin = 20v, bat = 16v charge current (a) 0 80 efficiency (%) power loss(mw) 85 90 100 100 1000 10000 0.5 1 1.5 2 4012 g03 2.5 3 95 efficiency power loss r sense = 33m r in = 3.01k clp pin voltage (v) 5 v fb error (%) 0.02 0.06 0.10 25 4012 g04 ?0.02 ?0.06 0 0.04 0.08 ?0.04 ?0.08 ?0.10 10 15 20 30 ltc4012 test circuit battery voltage (v) 0 75 r on () 100 150 175 200 10 20 25 300 4012 g05 125 5 15 225 250 275 clp = bat + 3v (clp 6v) fbdiv pin r on vs battery voltage (t a = 25c unless otherwise noted. l = ihlp-2525 6.8h) charge current accuracy battery voltage (v) 0 ?6 charge current error (%) ?4 ?3 ?2 108 20 2422 2 4012 g07 ?5 642 1412 16 18 ?1 0 1 dcin = 12v r prog = 26.7k dcin = 24v r prog = 35.7k r sense = 33m r in = 3.01k
4012fa ltc4012/ ltc4012-1/ltc4012-2 t ypical p er f or m ance c haracteristics pwm frequency vs duty cycle gate drive non-overlap battery shutdown current charge current line regulation input current limit dcin pin voltage (v) 5 ?0.5 charge current error (%) ?0.4 ?0.2 ?0.1 0 0.5 0.2 10 15 4012 g08 ?0.3 0.3 0.4 0.1 20 25 i chg = 1a i chg = 2a i chg = 3a bat = 6v r sense = 33m r in = 3.01k charge current load regulation battery voltage (v) 11.0 charge current (a) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?0.5 12.6 4012 g09 11.4 11.8 12.2 13.0 i chg = 3a i chg = 2a i chg = 1a dcin = 20v r sense = 33m r in = 3.01k system load (a) 0 current (a) 0.5 1.0 1.5 1.5 2.5 4012 g10 0 ?0.5 ?1.0 0.5 1.0 2.0 2.0 2.5 3.0 i in i chg icl state 2.5a bulk charge 2.1a input current limit pwm soft-start i chg 2a/div time (500s/div) 4012 g11 ith 1v/div prog 1v/div shdn 5v/div time (80ns/div) external fet drive (1v/div) 4012 g12 tgate bgate duty cycle (%) 0 0 pwm frequency (khz) 100 200 300 400 500 600 20 40 60 80 4012 g13 100 clp = 6v clp = 12v clp = 20v clp = 25v i chg = 750ma pwm frequency vs charge current charge current (a) 0 0 pwm frequency (khz) 100 200 300 400 600 0.5 1.0 1.5 2.0 4012 g14 2.5 3.0 500 bat = 14.5v bat = 12v bat = 5v clp = 15v r sense = 33m r in = 3.01k battery voltage (v) 0 0 battery current (a) 5 10 15 25 5 10 15 4012 g15 20 25 20 dc1256-class application dcin = 0v ltc4012, all pins dcin = 0v ltc4012, bat pins dcin = 20v (t a = 25c unless otherwise noted. l = ihlp-2525 6.8h) infet response time to dcin short to ground 0a v gs = 0v time (1s/div) dcin = 15v infet = si7423dn i out = <50ma v out = 12.3v c out = 0.27f 4012 g16 pfet v gs (1v/div) i dcin, reverse (5a/div)
ltc4012/ ltc4012-1/ltc4012-2 4012fa p in functions cln (pin 1): adapter input current limit negative input. the ltc4012 senses voltage on this pin to determine if less charge current should be sourced to limit total input current. the threshold is set 100mv below the clp pin. an external filter should be used to remove switching noise. this input should be tied to clp if not used. operating voltage range is (clp C 110mv) to clp. clp (pin 2): adapter input current limit positive input. the ltc4012 also draws power from this pin, including a small amount for some shutdown functions. operating voltage range is gnd to 28v. infet (pin 3): powerpath control output. this output drives the gate of a pmos pass transistor connected between the dc input (dcin) and the raw system supply rail (clp) to maintain a forward voltage of 25mv when a dc input source is present. infet is internally clamped about 6v below clp. maximum operating voltage is clp, which is used to turn off the input pmos transistor when the dc input is removed. dcin (pin 4): dc sense input. one of two voltage sense inputs to the internal powerpath controller (the other input to the controller is clp). this input is usually supplied from an input dc power source. operating voltage ranges from gnd to 28.2v. acp (pin 5): active-low ac adapter present indicator output. this open-drain output pulls to gnd when adequate ac adapter (dcin) voltage is present. this output should be left floating if not used. shdn ( pin 6): active-low shutdown input. driving shdn below 300mv unconditionally forces the ltc4012 into the shutdown state. this input has a 40k internal pulldown to gnd. operating voltage range is gnd to intv dd . chrg (pin 7): active-low charge indicator output. this open-drain output provides three levels of information about charge status using a strong pull-down, 25a weak pull-down or high impedance. refer to the operation and applications information sections for further details. this output should be left floating if not used. icl (pin 8): active-low input current limit indicator out- put. this open-drain output pulls to gnd when the charge current is reduced because of ac adapter input current limiting. this output should be left floating if not used. v fb (pin 9, ltc4012): battery voltage feedback input. an external resistor divider between fbdiv and gnd with the center tap connected to v fb programs the charger output voltage. in constant voltage mode, this pin is nominally at 1.2085v. refer to the applications information section for complete details on programming battery voltage. operating voltage range is gnd to 1.25v. fvs0 (pin 9, ltc4012-1/ltc4012-2): battery voltage select input (lsb). this pin is one of two pins used on the ltc4012-1 or ltc4012-2 to select one of four preset battery voltages. selection is done by connecting to either gnd or intv dd . operating voltage range is gnd to intv dd . fbdiv (pin 10, ltc4012): battery voltage feedback resistor divider source. the ltc4012 connects this pin to bat when charging is in progress. fbdiv is an open- drain pfet output to bat with an operating voltage range of gnd to bat. fvs1 (pin 10, ltc4012-1/ltc4012-2): battery voltage select input (msb). this pin is one of two pins used on the ltc4012-1 or ltc4012-2 to select one of four preset battery voltages. selection is done by connecting to either gnd or intv dd . operating voltage range is gnd to intv dd . bat (pin 11): battery pack connection. the ltc4012 uses the voltage on this pin to control pwm operation when charging. operating voltage range is gnd to cln. ith (pin 12): pwm control voltage and compensation node. the ltc4012 develops a voltage on this pin to control cycle-by-cycle peak inductor current. an external r-c network connected to ith provides pwm loop com- pensation. refer to the applications information section for further details on establishing loop stability. operating voltage range is gnd to intv dd .
4012fa ltc4012/ ltc4012-1/ltc4012-2 p in functions prog (pin 13): charge current programming and monitor- ing pin. an external resistance connected between prog and gnd, along with the current sense and pwm input resistors, programs the maximum charge current. the voltage on this pin can also provide a linearized indicator of charge current. refer to the applications information section for complete details on current programming and monitoring. operating voltage range is gnd to intv dd . csn (pin 14): charge current sense negative in- put. place an external input resistor (r in , figure 1) between this pin and the negative side of the charge current sense resistor. operating voltage ranges from (bat C 50mv) to (bat + 200mv). csp (pin 15): charge current sense positive input. place an external input resistor (r in , figure 1) be- tween this pin and the positive side of the charge current sense resistor. operating voltage ranges from (bat C 50mv) to (bat + 200mv). bgate (pin 16): external synchronous nfet gate control output. this output provides gate drive to an external nmos power transistor switch used for synchronous rectification to increase efficiency in the step-down dc/dc converter. operating voltage is gnd to intv dd . bgate should be left floating if not used. intv dd (pin 17): internal 5v regulator output. this pin provides a means of bypassing the internal 5v regulator used to power the ltc4012 pwm fet drivers. this supply shuts down when the ltc4012 shuts down. refer to the application information section for details if additional power is drawn from this pin by the application circuit. sw (pin 18): pwm switch node. the ltc4012 uses the voltage on this pin as the source reference for its topside nfet (pwm switch) driver. refer to the applications in- formation section for additional pcb layout suggestions related to this critical circuit node. operating voltage range is gnd to cln. tgate (pin 19): external nfet switch gate control output. this output provides gate drive to an external nmos power transistor switch used in the dc/dc converter. operating voltage range is gnd to (cln + 5v). boost (pin 20): tgate driver supply input. a bootstrap capacitor is returned to this pin from a charge network connected to sw and intv dd . refer to the applications information section for complete details on circuit topol- ogy and component values. operating voltage ranges from (intv dd C 1v) to (cln + 5v). gnd (exposed pad pin 21): ground. the package paddle provides a single-point ground for the internal voltage reference and other critical ltc4012 circuits. it must be soldered to a suitable pcb copper ground pad for proper electrical operation and to obtain the specified package thermal resistance.
ltc4012/ ltc4012-1/ltc4012-2 0 4012fa b lock diagra m ? ? ? + ? + 19 ea r1 to internal circuits to internal circuits cc ? + ca 1.2085v reference 5v regulator pwm logic fault detection c/10 detection shutdown control oscillator bat shutdown charge input current limit tgate 20 boost 12 ith 13 prog 14 csn 15 csp 18 sw 21 gnd (paddle) 4012 bd01 16 bgate 17 intv dd to internal circiuts 11 v fb 9 chrg 7 fbdiv 10 acp 6 shdn icl 8 clp cln 2 1 infet 3 dcin 4 + ? if 5 (ltc4012)
4012fa ltc4012/ ltc4012-1/ltc4012-2 b lock diagra m (ltc4012-1/ltc4012-2) ? ? ? + ? + 19 ea r1 to internal circuits to internal circuits cc ? + ca 1.2085v reference 5v regulator pwm logic output voltage select fault detection c/10 detection shutdown control oscillator bat fvs0 fvs1 shutdown charge input current limit tgate 20 boost 12 ith 13 prog 14 csn 15 csp 18 sw p gnd (paddle) 4012 bd02 16 bgate 17 intv dd to internal circiuts chrg 7 10 9 11 5 acp 6 shdn icl 8 clp cln 2 1 infet 3 dcin 4 + ? if v fb
ltc4012/ ltc4012-1/ltc4012-2 4012fa o peration overview the ltc4012 is a synchronous step-down (buck) current mode pwm battery charger controller. the maximum charge current is programmed by the combination of a charge current sense resistor (r sense ), matched input resistors (r in , figure 1), and a programming resis- tor (r prog ) between the prog and gnd pins. battery voltage is programmed with an external resistor divider between fbdiv and gnd (ltc4012) or two digital battery voltage select pins (ltc4012-1/ltc4012-2). in addition, the prog pin provides a linearized voltage output of the actual charge current. the ltc4012 family does not have built-in charge termina- tion and is flexible enough for charging any type of battery chemistry. these are building block ics intended for use with an external circuit, such as a microcontroller, capable of managing the entire algorithm required for the specific battery being charged. each member of the ltc4012 fam- ily features a shutdown input and various state indicator outputs, allowing easy and direct management by a wide range of external (digital) charge controllers. due to the popularity of rechargeable lithium-ion chemistries, the ltc4012-1 and ltc4012-2 also offer internal precision resistors that can be digitally selected to produce one of four preset output voltages for simplified design of those charger types. shutdown the ltc4012 remains in shutdown until dcin is greater than 5.1v and exceeds clp by 60mv and shdn is driven above 1.4v. in shutdown, current drain from the battery is reduced to the lowest possible level, thereby increasing standby time. when in shutdown, the ith pin is pulled to gnd and chrg, icl , fet gate drivers and intv dd output are all disabled. the charging can be stopped at any time by forcing shdn below 300mv. ac present indication the acp status output correctly indicates sensed adapter input voltage during all ltc4012 states. ac present is indicated ( acp output low) as soon as dcin exceeds bat by at least 500mv. charging is not enabled until this condition is first met. after this event, charging is no longer gated by ac present detection. if battery voltage rises due to esr, or dcin droops due to current load, ac present may no longer be indicated by the ic if charging was started with very low input overhead. however, charging will remain enabled unless dcin falls below the supply voltage on clp. input powerpath control the input pfet controller performs many important func- tions. first, it monitors dcin and enables the charger when this input voltage is higher than the raw clp sys- tem supply. next, it controls the gate of an external input power pfet to maintain a low forward voltage drop when charging, creating improved efficiency. it also prevents reverse current flow through this same pfet, providing a suitable input blocking function. finally, it helps avoid synchronous boost operation during invalid operating conditions by detecting elevated clp voltage and forcing the charger off. if dcin voltage is less than clp, then dcin must rise 60mv higher than clp to enable the charger and activate the ideal diode control. at this point, the acpb status output also transitions to low impedance to indicate to the host system that an external adapter is present. the gate of the input pfet is driven to a voltage sufficient to regulate a forward drop between dcin and clp of about 25mv. if the input voltage differential drops below this point, the fet is turned off slowly. if the voltage between dcin and clp drops to less than C25mv, the input fet is turned off in less than 6s to prevent significant reverse current from flowing back through the pfet. in this case, acpb also switches back to high impedance and the charger is disabled. soft-start exiting the shutdown state enables the charger and releases the ith pin. when enabled, switching will not begin until dcin exceeds bat by 500mv and ith exceeds a threshold that assures initial current will be positive (about 5% to 25% of the maximum programmed current). to limit inrush current, soft-start delay is created with the compensation values used on the ith pin. longer soft-start times can be realized by increasing the filter capacitor on ith, if reduced loop bandwidth is acceptable. the actual charge current at
4012fa ltc4012/ ltc4012-1/ltc4012-2 the end of soft-start will depend on which loop (current, voltage or adapter limit) is in control of the pwm. if this current is below that required by the ith start-up threshold, the resulting charge current transient duration depends on loop compensation but is typically less than 100s. bulk charge when soft-start is complete, the ltc4012 begins sourc- ing the current programmed by the external components connected to csp, csn and prog. some batteries may require a small conditioning trickle current if they are heav- ily discharged. as shown in the applications information section, the lt4012 can address this need through a variety of low current circuit techniques on the prog pin. once a suitable cell voltage has been reached, charge current can be switched to a higher, bulk charge value. end of charge and chrg output as the battery approaches the programmed output volt- age, charge current will begin to decrease. the open-drain chrg output can indicate when the current drops to 10% of its programmed full-scale value by turning off the strong pull-down (open-drain fet) and turning on a weak 25a pull-down current. this weak pull-down state is latched until the part enters shutdown or the sensed current rises to roughly c/6. c/10 indication will not be set if charge current has been reduced due to adapter input current limiting. as the charge current approaches 0a, the pwm continues to operate in full continuous mode. this avoids generation of audible noise, allowing bulk ceramic capaci- tors to be used in the application. charge current monitoring when the ltc4012 is charging, the voltage on the prog pin varies in direct proportion to the charge current. referring to figure 1, the nominal prog voltage is given by v i r r r a r prog chrg sense prog in prog = + ? ? . ?11 67 voltage tolerance on prog is limited by the charge current accuracy specified in the electrical characteristics table. refer to the applications information section on program- ming charge current for additional details. o peration figure 1. pwm circuit diagram ? ? ? + ? + ea ca ? + cc 19 2 11 pwm logic oscillator watchdog timer loop compensation tgate system power l1 r in + ? 16 bgate 15 csp 14 csn 13 prog 9 v fb 12 ith r prog r1 from icl 1.2085v r sense v sense i chrg 4012 f01 c prog qs clock ltc4012 clp bat r d r in +
ltc4012/ ltc4012-1/ltc4012-2 4012fa adapter input current limit the ltc4012 can monitor and limit current from the input dc supply, which is normally an ac adapter. when the programmed adapter input current is reached, charge current is reduced to maintain the desired maximum input current. the ith and prog pins will reflect the reduced charge current. this limit function avoids overloading the dc input source, allowing the product to operate at the same time the battery is charging without complex load management algorithms. the battery will automatically be charged at the maximum possible rate that the adapter will support, given the applications operating condition. the ltc4012 can only limit input current by reducing charge current, and in this case the charger uses nonsynchro- nous pwm operation to prevent boosting if the average charge current falls below about 25% of the maximum programmed current. note that the icl indicator output becomes active (low) at an adapter input current level just slightly less than that required for the internal amplifier to begin to assert control over the pwm loop. charger status indicator outputs the ltc4012 open-drain indicator outputs provide valu- able information about the ics operating state and can be used for a variety of purposes in applications. table 1 summarizes the state of the three indicator outputs as a function of ltc4012 operation. o peration table 1. ltc4012 open-drain indicator outputs acp chrg icl charger state off off off no dc input (shutdown) on off off shutdown or reverse current on on off bulk charge on 25a off low current charge or initial dcin C bat <500mv on on on input current limit during bulk charge on 25a on input current limit during low current charge off on or 25a on or off indicated charge with dcin - bat < 300mv. bulk charge may be less than programmed value. pwm controller the ltc4012 uses a synchronous step-down architec- ture to produce high operating efficiency. the nominal operating frequency of 550khz allows use of small filter components. the following conceptual discussion of basic pwm operation references figure 1. the voltage across the external charge current sense resistor r sense is measured by current amplifier ca. this instantaneous current (v sense /r in ) is fed to the prog pin where it is averaged by an external capacitor and converted to a voltage by the programming resistor r prog between prog and gnd. the prog voltage becomes the aver- age charge current input signal to error amplifier ea. ea also receives loop control information from the battery voltage feedback input v fb and the adapter input current limit circuit. figure 2. pwm waveforms on off off inductor current top fet bottom fet on t off threshold set by ith voltage 4012 f02
4012fa ltc4012/ ltc4012-1/ltc4012-2 the ith output of the error amplifier is a scaled control voltage for one input of the pwm comparator cc. ith sets a peak inductor current threshold, sensed by r1, to maintain the desired average current through r sense . the current comparator output does this by switching the state of the rs latch at the appropriate time. at the beginning of each oscillator cycle, the pwm clock sets the rs latch and turns on the external top- side nfet (bottom-side synchronous nfet off) to refresh the current carried by the external inductor l1. the inductor current and voltage across r sense begin to rise linearly. ca buffers this instantaneous voltage rise and applies it to cc with gain supplied by r1. when the voltage across r1 exceeds the peak level set by the ith output of ea, the top fet turns off and the bottom fet turns on. the inductor current then ramps down lin- early until the next rising pwm clock edge. this closes the loop and sources the correct inductor current to maintain the desired parameter (charge current, battery voltage, or input current). to produce a near constant frequency, the pwm oscillator implements the equation: t clp bat clp khz off = ? ? 550 repetitive, closed-loop waveforms for stable pwm opera- tion appear in figure 2. pwm watchdog timer as input and output conditions vary, the ltc4012 may need to utilize pwm duty cycles approaching 100%. in this case, operating frequency may be reduced well below 550khz. an internal watchdog timer observes the activity on the tgate pin. if tgate is on for more than 40s, the watchdog activates and forces the bottom nfet on (top nfet off) for about 100ns. this avoids a potential source of audible noise when using ceramic input or output capacitors and prevents the boost supply capacitor for the top gate driver from discharging. in low drop out operation, the actual charge current may not be able to reach the programmed full-scale value due to the watchdog function. overvoltage protection the ltc4012 also contains overvoltage detection that prevents transient battery voltage overshoots of more than about 6% above the programmed output voltage. when battery overvoltage is detected, both external mosfets are turned off until the overvoltage condition clears, at which time a new soft start sequence begins. this is useful for properly charging battery packs that use an internal switch to disconnect themselves for performing functions such as calibration or pulse mode charging. reverse charge current protection (anti-boost) because the ltc4012 always attempts to operate syn- chronously in full continuous mode (to avoid audible noise from ceramic capacitors), reverse average charge current can occur during some invalid operating condi- tions. infet powerpath control avoids boosting a lightly loaded system supply during reverse operation. however, under heavier system loads, clp may not boost above dcin, even though reverse average current is flowing. in this case a second circuit monitors indication of reverse average current on prog. if either of these circuits detects boost operation, the ltc4012 turns off both external mosfets until the reverse current condition clears. at that point, a new soft-start sequence begins. o peration
ltc4012/ ltc4012-1/ltc4012-2 4012fa a pplications i n f or m ation programming charge current the formula for charge current is: i r r v r a chrg in sense prog = ? ? ? ? ? ? ? . ? . 1 2085 11 67 the ltc4012 operates best with 3.01k input resistors, although other resistors near this value can be used to accommodate standard sense resistor values. refer to the subsequent discussion on inductor selection for other considerations that come into play when selecting input resistors r in . r sense should be chosen according to the following equation: r mv i sense max = 100 where i max is the desired maximum charge current i chrg . the 100mv target can be adjusted to some degree to obtain standard r sense values and/or a desired r prog value, but target voltages lower than 100mv will cause a proportional reduction in current regulation accuracy. the required minimum resistance between prog and gnd can be determined by applying the suggested expression for r sense while solving the first equation given above for charge current with i chrg = i max : r v r v a r prog min in in ( ) . ? . . ? = + 1 2085 0 1 11 67 if r in is chosen to be 3.01k with a sense voltage of 100mv, this equation indicates a minimum value for r prog of 26.9k. table 6 gives some examples of recommended charge current programming component values based on these equations. the resistance between prog and gnd can simply be set with a single a resistor, if only maximum charge cur- rent needs to be controlled during the desired charging algorithm. however, some batteries require a low charge cur- rent for initial conditioning when they are heav- ily discharged. the charge current can then be safely switched to a higher level after conditioning is complete. figure 3 illustrates one method of doing this with 2-level control of the prog pin resistance. turning q1 off reduces the charge current to i max /10 for battery conditioning. when q1 is on, the ltc4012 is programmed to allow full i max current for bulk charge. this technique can be expanded through the use of additional digital control inputs for an arbitrary number of pre-programmed cur- rent values. for a truly continuous range of maximum charge current control, pulse width modulation can be used as shown in figure 4. figure 3. programming 2-level charge current 13 q1 2n7002 4012 f03 r2 53.6k prog ltc4012 r1 26.7k c prog 4.7nf bulk charge precharge figure 4. programming pwm current 13 q1 2n7002 4012 f04 prog ltc4012 r prog r max 511k c prog 0v 5v
4012fa ltc4012/ ltc4012-1/ltc4012-2 a pplications i n f or m ation the value of r prog controls the maximum value of charge current which can be programmed (q1 continuously on). pwm of the q1 gate voltage changes the value of r prog to produce lower currents. the frequency of this modula- tion should be higher than a few khz, and c prog must be increased to reduce the ripple caused by switching q1. in addition, it may be necessary to increase loop compensa- tion capacitance connected to ith to maintain stability or prevent large current overshoot during start-up. selecting a higher q1 pwm frequency (10khz) will reduce the need to change c prog or other compensation values. charge current will be proportional to the duty cycle of the pwm input on the gate of q1. programming ltc4012 output voltage figure 5 shows the external circuit for programming the charger voltage when using the ltc4012. the voltage is then governed by the following equation: v v r r r r r a r b bat = + ( ) = + 1 2085 1 2 2 2 2 2 . ? , see table 2 for approximate resistor values for r2. r r v r r a r b 1 2 1 2085 1 2 2 2 = ? ? ? ? ? ? = + v bat . ? , selecting r2 to be less than 50k and the sum of r1 and r2 at least 200k or above, achieves the lowest possible error at the v fb sense input. note that sources of error such as r1 and r2 tolerance, fbdiv r on or v fb input impedance are not included in the specifications given in the electrical characteristics. this leads to the possibil- ity that very accurate (0.1%) external resistors might be required. actually, the temperature rise of the ltc4012 will rarely exceed 50c at the end of charge, because charge current will have tapered to a low level. this means that 0.25% resistors will normally provide the required level of overall accuracy. table 2 gives recommended values for r1 and r2 for popular lithium-ion battery voltages. for values of r1 above 200k, addition of capacitor c z may improve transient response and loop stability. a value of 10pf is normally adequate. table 2. programming output voltage v bat (v) r1 (0.25%) (k) r2a (0.25%) (k) r2b (1%)* () 4.1 165 69 C 4.2 167 67.3 200 8.2 162 28 C 8.4 169 28.4 C 12.3 301 32.8 C 12.6 294 31.2 C 16.4 284 22.6 C 16.8 271 21 C 20.5 316 19.8 C 21 298 18.2 C 24.6 298 15.4 C 25.2 397 20 C *to obtain desired accuracy requires series resistors for r2. figure 5. programming output voltage 11 10 bat fbdiv 85 typical 9 v fb ltc4012 r1 r2a r2b* 4012 f05 c z 21 gnd (exposed pad) *optional trim resistor +
ltc4012/ ltc4012-1/ltc4012-2 4012fa a pplications i n f or m ation programming ltc4012-1/ltc4012-2 output voltage the ltc4012-1/ltc4012-2 feature precision internal bat- tery voltage feedback resistor taps configured for common lithium-ion voltages. all that is required to program the desired voltage is proper pin programming of fvs0 and fvs1 as shown in table 3. table 3. ltc4012-1/ltc4012-2 output voltage programming v bat voltage ltc4012-1 ltc4012-2 fvs1 fvs0 4.1v 4.2v gnd gnd 8.2v 8.4v gnd intv dd 12.3v 12.6v intv dd gnd 16.4v 16.8v intv dd intv dd programming input current limit to set the input current limit i lim , the minimum wall adapter current rating must be known. to account for the tolerance of the ltc4012 input current sense circuit, 5% should be subtracted from the adapters minimum rated output. refer to figure 6 and program the input current limit function with the following equation. r mv i cl lim = 100 where i lim is the desired maximum current draw from the dc (adapter) input, including adjustments for tolerance, if any. figure 6. programming input current limit 2 1 r cl c dc c f 0.1f clp ltc4012 cln r f 5.1k 4012 f06 10k from dc power input to remainder of system 3 infet 2 1 clp cln 17 intv dd ltc4012 r cl 1% r3 = r1 1% r1 1% q2 2sc2412 r f 2.49k 1% r2 q1 imx1 4012 f07 c f 0.22f to remainder of system from infet figure 7. adjusting input current limit often an ac adapter will include a rated current output margin of at least +10%. this can allow the adapter cur- rent limit value to simply be programmed to the actual minimum rated adapter output current. table 4 shows some common r cl current limit programming values. a lowpass filter formed by r f (5.1k) and c f (0.1f) is required to eliminate switching noise from the ltc4012 pwm and other system components. if input current limit- ing is not desired, cln should be shorted to clp while clp remains connected to power. table 4. common r cl values adapter rating (a) r cl value (1%) () r cl power dissipation (w) r cl power rating (w) 1.00 0.100 0.100 0.25 1.25 0.080 0.125 0.25 1.50 0.068 0.150 0.25 1.75 0.056 0.175 0.25 2.00 0.050 0.200 0.25 2.50 0.039 0.244 0.50 3.00 0.033 0.297 0.50 3.50 0.027 0.331 0.50 4.00 0.025 0.400 0.50 figure 7 shows an optional circuit that can influence the parameters of the input current limit in two ways.
4012fa ltc4012/ ltc4012-1/ltc4012-2 a pplications i n f or m ation the first option is to lower the power dissipation of r cl at the expense of accuracy without changing the input current limit value. the second is to make the input current limit value programmable. the overall accuracy of this circuit needs to be better than the power source current tolerance or be margined such that the worse-case error remains under the power source limits. the accuracy of the figure 7 circuit is a function of the intv dd , v be , r cl , r f , r1 and r3 tolerances. to improve accuracy, the tolerance of r f should be changed from 5.1k, 5% to a 2.49k 1% resistor. r cl and the programming resistors r1 and r3 should also be 1% tolerance such that the dominant error is intv dd (3%). bias resistor r2 can be 5%. when choosing npn transistors, both need to have good gain (>100) at 10a levels. low gain npns will increase programming errors. q1 must be a matched npn pair. since r f has been reduced in value by half, the capacitor value of c f should double to 0.22f to remain effective at filtering out any noise. if you wish to reduce r cl power dissipation for a given current limit, the programming equation becomes: r mv k r i cl lim = ? ? ? ? ? ? 100 5 2 49 1 ? ? . if you wish to make the input current limit programmable, the equation becomes: i mv k r r lim cl = ? ? ? ? ? ? 100 5 2 49 1 ? ? . the equation governing r2 for both applications is based on the value of r1. r3 should always be equal to r1. r2 = 0.875 ? r1 figure 8. prog voltage buffer 17 13 intv dd prog <30na ltc4012 4012 f08 to system monitor + ? in many notebook applications, there are situations where two different i lim values are needed to allow two different power adapters or power sources to be used. in such cases, start by setting r lim for the high power i lim configuration and then use figure 7 to set the lower i lim value. to toggle between the two i lim values, take the three ground connections shown in figure 7, combine them into one common connection and use a small-signal nfet (2n7002) to open or close that common connec- tion to circuit ground. when the nfet is off, the circuit is defeated (floating) allowing i lim to be the maximum value. when the nfet is on, the circuit will become active and i lim will drop to the lower set value. monitoring charge current the prog pin voltage can be used to indicate charge cur- rent where 1.2085v indicates full programmed current (1c) and zero charge current is approximately equal to r prog ? 11.67a. prog voltage varies in direct proportion to the charge current between this zero-current (offset) value and 1.2085v. when monitoring the prog pin voltage, using a buffer amplifier as shown in figure 8 will minimize charge current errors. the buffer amplifier may be powered from the intv dd pin or any supply that is always on when the charger is on.
ltc4012/ ltc4012-1/ltc4012-2 0 4012fa a pplications i n f or m ation table 5. digital read back state (in, figure 10) ltc4012 charger state out state hi-z 1 off 1 1 c/10 charge 0 1 bulk charge 0 0 input and output capacitors in addition to typical input supply bypassing (0.1f) on dcin, the relatively high esr of aluminum electrolytic ca- pacitors is helpful for reducing ringing when hot-plugging the charger to the ac adapter. refer to ltc application note 88 for more information. the input capacitor between system power (drain of top fet, figure 1) and gnd is required to absorb all input pwm ripple current, therefore it must have adequate ripple current rating. maximum rms ripple current is typically one-half of the average battery charge current. actual capacitance value is not critical, but using the highest possible voltage rating on pwm input capacitors will minimize problems. consult with the manufacturer before use. figure 10. microprocessor status interface 33k 200k 4012 f10 v dd 3.3v p in out ltc4012 chrg 7 c/10 chrg indicator the value chosen for r prog has a strong influence on charge current monitoring and the accuracy of the c/10 charge indicator output ( chrg ). the ltc4012 uses the voltage on the prog pin to determine when charge current has dropped to the c/10 threshold. the nominal threshold of 400mv produces an accu- rate low charge current indication of c/10 as long as r prog = 26.7k, independent of all other current pro- gramming considerations. however, it may sometimes be necessary to deviate from this value to satisfy other application design goals. if r prog is greater than 26.7k, the actual level at which low charge current is detected will be less than c/10. the highest value of r prog that can be used while reliably indicating low charge current before reaching final v bat is 30.1k. r prog can safely be set to values higher than this, but low current indication will be lost. if r prog is less than 26.7k, low charge current detection occurs at a level higher than c/10. more importantly, the ltc4012 becomes increasingly sensitive to reverse cur- rent. the lowest value of r prog that can be used without the risk of erroneous boost operation detection at end of charge is 26.1k. values of r prog less than this should not be used. see the operation section for more information about reverse current. the nominal fractional value of i max at which c/10 indica- tion occurs is given by: i i mv r a v r c max prog prog 10 400 11 67 1 2085 = ( ) ? ? . . ? ?? .11 67a ( ) direct digital monitoring of c/10 indication is possible with an external application circuit like the one shown in figure 9. by using two different value pull-up resistors, a micropro- cessor can detect three states from this pin (charging, c/10 and not charging). see figure 10. when a digital output port (out) from the microprocessor drives one of the resistors and a second digital input port polls the network, the charge state can be determined as shown in table 5. figure 9. digital c/10 indicator 17 7 intv dd chrg q1 tp0610t q2 2n7002 100k ltc4012 4012 f09 100k v logic 100k c/10 chrg 100k q3 2n7002
4012fa ltc4012/ ltc4012-1/ltc4012-2 the output capacitor shown across the battery and ground must also absorb pwm output ripple current. the general formula for this capacitor current is: i v v v l f rms bat bat clp pwm = ? ? ? ? ? ? 0 29 1 1 . ? ? ? ? for example, i rms = 0.22a with: v bat = 12.6v v clp = 19v l1 = 10h f pwm = 550khz high capacity ceramic capacitors (20f or more) available from a variety of manufacturers can be used for input/out- put capacitors. other alternatives include os-con and poscap capacitors from sanyo. low esr solid tantalum capacitors have high ripple cur- rent rating in a relatively small surface mount package, but exercise caution when using tantalum for input or output bulk capacitors. high input surge current can be created when the adapter is hot-plugged to the charger or when a battery is connected to the charger. solid tan- talum capacitors have a known failure mechanism when subjected to very high surge currents. select tantalum capacitors that have high surge current ratings or have been surge tested. emi considerations usually make it desirable to minimize ripple current in battery leads. adding ferrite beads or inductors can increase battery impedance at the nominal 550khz switching frequency. switching ripple current splits between the battery and the output capacitor in inverse relation to capacitor esr and the battery impedance. if the esr of the output capacitor is 0.2 and the battery impedance is raised to 4 with a ferrite bead, only 5% of the current ripple will flow to the battery. inductor selection higher switching frequency generally results in lower efficiency because of mosfet gate charge losses, but it allows smaller inductor and capacitor values to be used. a primary effect of the inductor value l1 is the amplitude of ripple current created. the inductor ripple current ?i l decreases with higher inductance and pwm operating frequency: ? i v v v l f l bat bat clp pwm = ? ? ? ? ? ? ? ? ? 1 1 accepting larger values of ?i l allows the use of low in- ductance, but results in higher output voltage ripple and greater core losses. lower charge currents generally call for larger inductor values. the ltc4012 limits maximum instantaneous peak inductor current during every pwm cycle. to avoid unstable switch waveforms, the ripple current must satisfy: ? i mv r i l sense max < ? ? ? ? ? ? 2 150 ? ? so choose: l v f mv r i clp pwm sense max 1 0 125 150 > ? ? ? ? ? ? . ? ? ? for c-grade parts, a reasonable starting point for setting ripple current is ?i l = 0.4 ? i max . for i-grade parts, use ?i l = 0.2 ? i max only if the ic will actually be used to charge batteries over the wider i-grade temperature range. the voltage compliance of internal ltc4012 circuits also imposes limits on ripple current. select r in (in figure 1) to avoid average current errors in high ripple designs. the following equation can be used for guidance: r i a r r i a sense l in sense l ? ? ? ? 50 20 a pplications i n f or m ation
ltc4012/ ltc4012-1/ltc4012-2 4012fa r in should not be less than 2.37k or more than 6.04k. val- ues of r in greater than 3.01k may cause some reduction in programmed current accuracy. use these equations and guidelines, as represented in table 6, to help select the cor- rect inductor value. this table was developed for c-grade p a rts to maintain maximum ? i l near 0.6 ? i max with f pwm at 550khz and v bat = 0.5 ? v clp (the point of maximum ?i l ), assuming that inductor value could also vary by 25% at i max . for i-grade parts, reduce maximum ?i l to less than 0.4 ? i max , but only if the ic will actually be used to charge batteries over the wider i-grade temperature range. in that case, a good starting point can be found by multiplying the inductor values shown in table 6 by a factor of 1.6 and rounding up to the nearest standard value. table 6. minimum typical inductor values v clp l1 (typ) i max r sense r in r prog <10v 10h 1a 100m 3.01k 26.7k 10v to 20v 20h 1a 100m 3.01k 26.7k >20v 28h 1a 100m 3.01k 26.7k <10v 5.1h 2a 50m 3.01k 26.7k 10v to 20v 10h 2a 50m 3.01k 26.7k >20v 14h 2a 50m 3.01k 26.7k <10v 3.4h 3a 33m 3.01k 26.7k 10v to 20v 6.8h 3a 33m 3.01k 26.7k >20v 9.5h 3a 33m 3.01k 26.7k <10v 2.5h 4a 25m 3.01k 26.7k 10v to 20v 5.1h 4a 25m 3.01k 26.7k >20v 7.1h 4a 25m 3.01k 26.7k to guarantee that a chosen inductor is optimized in any given application, use the design equations provided and perform bench evaluation in the target application, par- ticularly at duty cycles below 20% or above 80% where pwm frequency can be much less than the nominal value of 550khz. tgate boost supply use the external components shown in figure 11 to de- velop a bootstrapped boost supply for the tgate fet driver. a good set of equations governing selection of the two capacitors is: c q v c c g 1 20 4 5 2 20 1 = = ? . , ? where q g is the rated gate charge of the top external nfet with v gs = 4.5v. the maximum average diode current is then given by: i d = q g ? 665khz to improve efficiency by increasing v gs applied to the top fet, substitute a schottky diode with low reverse leakage for d1. pwm jitter has been observed in some designs operating at higher v in /v out ratios. this jitter does not substantially affect dc charge current accuracy. a series resistor with a value of 5 to 20 can be inserted between the cathode of d1 and the boost pin to remove this jitter, if present. a resistor case size of 0603 or larger is recommended to lower esl and achieve the best results. a pplications i n f or m ation figure 11. tgate boost supply 20 17 boost intv dd 18 sw ltc4012 4012 f11 c2 2f c1 0.1f l1 to r sense d1 1n4148
4012fa ltc4012/ ltc4012-1/ltc4012-2 a pplications i n f or m ation fet selection two external power mosfets must be selected for use with the charger: an n-channel power switch (top fet) and an n-channel synchronous rectifier (bottom fet). peak gate-to-source drive levels are internally set to about 5v. consequently, logic-level fets must be used. in addition to the fundamental dc current, selection criteria for these mosfets also include channel resis- tance r ds(on) , total gate charge q g , reverse transfer capacitance c rss , maximum rated drain-source voltage bv dss and switching characteristics such as t d(on/off) . power dissipation for each external fet is given by: p v i t r v k v d top bat max ds on clp c ( ) ( ) ? ? ? = + ( ) + 2 1 ? llp max rss d bot clp bat m i c khz p v v i 2 665 ? ? ? ? ? ( ) = ( ) aax ds on clp t r v 2 1? ( ) + ( ) ? where is the temperature dependency of r ds(on) , ? t is the temperature rise above the point specified in the fet data sheet for r ds(on) and k is a constant in- versely related to the internal ltc4012 top gate driver. the term (1 + ? t) is generally given for a mosfet in the form of a normalized r ds(on) curve versus temperature, but of 0.005/c can be used as a suitable approxima- tion for logic-level fets if other data is not available. c rss = ?q gd / ? v ds is usually specified in the mosfet characteristics. the constant k = 2 can be used in estimat- ing top fet dissipation. the ltc4012 is designed to work best with external fet switches with a total gate charge at 5v of 15nc or less. for v clp < 20v, high charge current efficiency generally improves with larger fets, while for v clp > 20v, top gate transition losses increase rapidly to the point that using a topside nfet with higher r ds(on) but lower c rss can actually provide higher efficiency. if the charger will be operated with a duty cycle above 85%, overall efficiency is normally improved by using a larger top fet. the synchronous (bottom) fet losses are greatest at high input voltage or during a short circuit, which forces a low side duty cycle of nearly 100%. increasing the size of this fet lowers its losses but increases power dissipation in the ltc4012. using asymmetrical fets will normally achieve cost savings while allowing optimum efficiency. select fets with bv dss that exceeds the maximum v clp voltage that will occur. both fets are subjected to this level of stress during operation. many logic-level mosfets are limited to 30v or less. the ltc4012 uses an improved adaptive tgate and bgate drive that is insensitive to mosfet inertial delays, t d(on/off) , to avoid overlap conduction losses. switching characteristics from power mosfet data sheets apply only to a specific test fixture, so there is no substitute for bench evaluation of external fets in the target application. in general, mosfets with lower inertial delays will yield higher efficiency. diode selection a schottky diode in parallel with the bottom fet and/or top fet in an ltc4012 application clamps sw during the non-overlap times between conduction of the top and bottom fet switches. this prevents the body diode of the mosfets from forward biasing and storing charge, which could reduce efficiency as much as 1%. one or both diodes can be omitted if the efficiency loss can be tolerated. a 1a schottky is generally a good size for 3a chargers due to the low duty cycle of the non-overlap times. larger diodes can actually result in additional efficiency (transition) losses due to larger junction capacitance. loop compensation and soft-start the three separate pwm control loops of the ltc4012 can be compensated by a single set of components at- tached between the ith pin and gnd. as shown in the typical ltc4012 application, a 6.04k resistor in series with a capacitor of at least 0.1f provides adequate loop compensation for the majority of applications.
ltc4012/ ltc4012-1/ltc4012-2 4012fa figure 12. high speed switching path 4012 f12 v bat l1 r sense high frequency circulating path bat analog ground system ground switch node c in switching ground c out v in gnd d1 + the ltc4012 can be soft-started with the compensation capacitor on the ith pin. at start-up, ith will quickly rise to about 0.25v, then ramp up at a rate set by the com- pensation capacitor and the 40a ith bias current. the full programmed charge current will be reached when ith reaches approximately 2v. with a 0.1f capacitor, the time to reach full charge current is usually greater than 1.5ms. this capacitor can be increased if longer start-up times are required, but loop bandwidth and dynamic response will be reduced. intv dd regulator output bypass the intv dd regulator output to gnd with a low esr x5r or x7r ceramic capacitor with a value of 0.47f or larger. the capacitor used to build the boost supply (c2 in figure 11) can serve as this bypass. do not draw more than 30ma from this regulator for the host system, governed by ic power dissipation. calculating ic power dissipation the user should ensure that the maximum rated junction temperature is not exceeded under all operating conditions. the thermal resistance of the ltc4012 package ( ja ) is 37c/w, provided the exposed pad is in good thermal contact with the pcb. the actual thermal resistance in the application will depend on forced air cooling and other heat sinking means, especially the amount of copper on the pcb to which the ltc4012 is attached. the following formula may be used to estimate the maximum average power dis- sipation p d (in watts) of the ltc4012, which is dependent upon the gate charge of the external mosfets. this gate charge, which is a function of both gate and drain voltage swings, is determined from specifications or graphs in the manufacturers data sheet. for the equation below, find the gate charge for each transistor assuming 5v gate swing and a drain voltage swing equal to the maximum v clp voltage. maximum ltc4012 power dissipation under normal op- erating conditions is then given by: p d = dcin(3ma + i dd + 665khz(q tgate + q bgate )) C 5i dd a pplications i n f or m ation where: i dd = average external intv dd load current, if any q tgate = gate charge of external top fet in coulombs q bgate = gate charge of external bottom fet in coulombs pcb layout considerations t o prevent magnetic and electrical field radiation and high frequency resonant problems, proper layout of the components connected to the ltc4012 is essential. refer to figure 12. for maximum efficiency, the switch node rise and fall times should be minimized. the following pcb design priority list will help insure proper topology. layout the pcb using this specific order. 1. input capacitors should be placed as close as possible to switching fet supply and ground connections with the shortest copper traces possible. the switching fets must be on the same layer of copper as the input capacitors. vias should not be used to make these connections. 2. place the ltc4012 close to the switching fet gate terminals, keeping the connecting traces short to produce clean drive signals. this rule also applies to ic supply and ground pins that connect to the switching fet source pins. the ic can be placed on the opposite side of the pcb from the switching fets.
4012fa ltc4012/ ltc4012-1/ltc4012-2 3. place the inductor input as close as possible to the switching fets. minimize the surface area of the switch node. make the trace width the minimum needed to support the programmed charge current. use no cop- per fills or pours. avoid running the connection on multiple copper layers in parallel. minimize capacitance from the switch node to any other trace or plane. 4. place the charge current sense resistor immediately adjacent to the inductor output, and orient it such that current sense traces to the ltc4012 are not long. these feedback traces need to be run together as a single pair with the smallest spacing possible on any given layer on which they are routed. locate any filter component on these traces next to the ltc4012, and not at the sense resistor location. 5. place output capacitors adjacent to the sense resistor output and ground. 6. output capacitor ground connections must feed into the same copper that connects to the input capacitor ground before connecting back to system ground. 7. connection of switching ground to system ground, or any internal ground plane, should be single-point. if the system has an internal system ground plane, a good way to do this is to cluster vias into a single star point to make the connection. 8. r oute analog ground as a trace tied back to the ltc4012 gnd paddle before connecting to any other ground. avoid using the system ground plane. a useful cad technique is to make analog ground a separate ground net and use a 0 resistor to connect analog ground to system ground. 9. a good rule of thumb for via count in a given high current path is to use 0.5a per via. be consistent when applying this rule. 10. if possible, place all the parts listed above on the same pcb layer. 11. c opper fills or pours are good for all power connections except as noted above in rule 3. copper planes on multiple layers can also be used in parallel. this helps with thermal management and lowers trace inductance, which further improves emi performance. 12. for best current programming accuracy, provide a kelvin connection from r sense to csp and csn. see figure 13 for an example. 13. it is important to minimize parasitic capacitance on the csp and csn pins. the traces connecting these pins to their respective resistors should be as short as possible. a pplications i n f or m ation figure 13. kelvin sensing of charge current to csp r in 4012 f13 direction of charging current r sense to csn r in
ltc4012/ ltc4012-1/ltc4012-2 4012fa p ackage description 4.00 0.10 4.00 0.10 note: 1. drawing is proposed to be made a jedec package outline mo-220 variation (wggd-1)?to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 2019 1 2 bottom view?exposed pad 2.00 ref 2.45 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uf20) qfn 01-07 rev a recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.00 ref 2.45 0.05 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 s 45 chamfer 2.45 0.10 2.45 0.05 uf package 20-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1710 rev a)
4012fa ltc4012/ ltc4012-1/ltc4012-2 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h istory rev date description page number a 3/10 i-grade parts added. reflected throughout the data sheet 1 to 28
ltc4012/ ltc4012-1/ltc4012-2 4012fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0610 ? printed in usa r elate d p arts part number description comments ltc4006 small, high efficiency, fixed voltage, lithium-ion battery chargers with termination complete charger for 3- or 4-cell li-ion batteries, ac adapter current limit and thermistor sensor, 16-pin ssop package ltc4007 high efficiency, programmable voltage, lithium-ion battery charger with termination complete charger for 3- or 4-cell li-ion batteries, ac adapter current limit, thermistor sensor and indicator outputs ltc4008/ltc4008-1 high efficiency, programmable voltage/current battery chargers constant-current/constant-voltage switching regulator, resistor voltage/current programming, thermistor sensor and indicator outputs, ac adapter current limit (omitted on 4008-1) ltc4009/ltc4009-1 ltc4009-2 high efficiency, multichemistry battery charger constant-current/constant-voltage switching regulator in a 20-lead qfn package, ac adapter current limit, indicator outputs ltc4411 2.6a low loss ideal diode no external mosfet, automatic switching between dc sources, 140m on resistance in thinsot tm package ltc4412/ltc4412hv low loss powerpath controllers very low loss replacement for power supply oring diodes using minimal external complements, operates up to 28v (36v for hv) ltc4413 dual 2.6a, 2.5v to 5.5v ideal diodes low loss replacement for oring diodes, 100m on resistance ltc4414 36v, low loss powerpath controller for large pfets low loss replacement for oring diodes, operates up to 36v ltc4416 dual low loss powerpath controllers low loss replacement for oring diodes, operates up to 36v, drives large pfets, programmable, autonomous switching t ypical a pplication 12.6v 4 amp charger clp from adapter 15v at 4a bulk charge c4 0.1f r8 5.1k r14 100k q5 r15 0* d1 7 4 2 3 1 20 19 18 d3 17 16 21 15 14 11 10 q1 9 r12 294k c10 10pf 5 8 12 13 6 r7 25m r9 3.01k c5 0.1f c6 2f q2 q3 d4 l1 4.7h r11 25m 12.6v li-ion battery dcin chrg c2 0.1f r1 3k r r4 6.04k r5 26.7k r6 53.6k ltc4012 acp icl shdn ith prog cln boost infet tgate sw intv dd bgate to/from mcu gnd csp csn bat fbdiv v fb c8 10f power to system to power system load when adapter is not present, use schottky diode d5 or the combination of r14, d6 and q4 d6 18v zener c1 0.1f c3 4.7nf c9 10f r10 3.01k r13 31.2k 4012 ta03 d3: cmdsh-3 d4: mbr230lsft1 q1: 2n7002 q2, q3: si7212dn or sia914dj or si4816bdy (omit d4) q4, q5: si7423dn l1: 1hlp-2525czer4r7m11 *: see tgate boost supply in applications information + d5 q4 or

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